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INTEGRATED CIRCUITS
DATA SHEET
SAA7151B Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
Product specification File under Integrated Circuits, IC02 April 1993
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
FEATURES * 8-bit performance on chip for luminance and chrominance signal processing for PAL, NTSC and SECAM standards * Separate 8-bit luminance and 8-bit chrominance input signals from Y/C, CVBS, S-Video (S-VHS or Hi8) sources * SCART signal insertion by means of RGB/YUV convertion; fast switch handling * Horizontal and vertical sync detection for all standards * Real time control output RTCO * Fast sync recovery of vertical blanking for VCR signals (bottom flutter compensation) * Controls via the I2C-bus * User programmable aperture correction (horizontal peaking) * Cross-colour reduction by chrominance comb-filtering (NTSC) or by special cross-colour cancellation (SECAM) * 8-bit quantization of output signals in 4:1:1 or 4:2:2 formats * 720 active samples per line
SAA7151B
* The YUV bus supports a data rate of 13.5 MHz (CCIR 601). - (864 x fH) for 50 Hz - (858 x fH) for 60 Hz * Compatible with memory-based features (line-locked clock) * One 24.576 MHz crystal oscillator for all standards GENERAL DESCRIPTION The SAA7151B is a digital multistandard colour-decoder having two 8-bit input channels, one for CVBS or Y, the other for chrominance or time-multiplexed colour-difference signals.
QUICK REFERENCE DATA SYMBOL VDD IDD VI VO Tamb PARAMETER supply voltage (pins 5, 18, 28, 37 and 52) total supply current (pins 5, 18, 28, 37 and 52) input levels output levels operating ambient temperature 0 - - MIN. 4.5 5 100 TYP. MAX. 5.5 250 TTL-compatible TTL-compatible 70 C V mA UNIT
ORDERING INFORMATION EXTENDED TYPE NUMBER SAA7151B Note 1. SOT188-2; 1996 December 16. PACKAGE PINS 68 PIN POSITION mini-pack PLCC MATERIAL plastic CODE SOT188(1)
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MUXC CPI SYIS GPSW2 test pins SCART FSI FSO VSS1 to VSS4 19, 38, 51, 67 COMPONENT PROCESSING; SCART INTERFACE CONTROL; FAST SWITCH INSERTION 68 44 65 32 24 25 1, 2 66 GPSW1
+5 V
VDD1 to VDD4
BLOCK DIAGRAM
Philips Semiconductors
5, 18, 28, 52
RESN
3
POWER-ON RESET
SAA7151A
45 to 50, 53, 54 CHROMINANCE PROCESSOR 55 to 62 OUTPUT INTERFACE 42 64 LUMINANCE PROCESSOR clock status 37 +5 V 36 35 33 SYNCHRONIZATION CLOCK 34 VDDA LFCO VSSA XTAL XTALI 39 4 27 Y output (Y7 to Y0) UV output (UV7 to UV0) HREF FEIN
CVBS0 to CVBS7
14 to 17 20 to 23
INPUT INTERFACE
CUV0 to CUV7
6 to 13
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
3
63 26 29 30 31 HCL HSY VS HS ODD CREF
STATUS REGISTER
SDA
40
I2C-BUS
SCL
41
CONTROL
43
IICSA LL27
MEH292
GPSW0
Product specification
SAA7151B
Fig.1 Block diagram (application circuits see Figs 17, 18 and 19).
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
PINNING SYMBOL SP AP RESN CREF VDD1 CUV0 CUV1 CUV2 CUV3 CUV4 CUV5 CUV6 CUV7 CVBS0 CVBS1 CVBS2 CVBS3 VDD2 VSS1 CVBS4 CVBS5 CVBS6 CVBS7 GPSW1 GPSW2 HCL LL27 VDD3 HSY VS HS RTCO XTAL XTALI VSSA LFCO VDDA VSS2 April 1993 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 +5 V supply input 2 ground 1 (0 V) DESCRIPTION connected to ground (shift pin for testing) connected to ground (action pin for testing) reset, active-LOW
SAA7151B
clock reference, sync from external to ensure in-phase signals on the Y-, CUV- and YUV-bus +5 V supply input 1
chrominance input data bits CUV7 to CUV0 (digitized chrominance signals in two's complement format from a S-Video source (S-VHS, Hi8) or time-multiplexed colour-difference signals from a YUV(RGB) source or both in combination)
CVBS lower input data bits CVBS3 to CVBS0 (CVBS with luminance, chrominance and all sync information in two's complement format)
CVBS upper input data bits CVBS7 to CVBS4 (CVBS with luminance, chrominance and all sync information in two's complement format) status bit output FSST0 or port 1 output for general purpose (programmable by subaddress 0C) status bit output FSST1 or port 2 output for general purpose (programmable by subaddress 0C) black level clamp pulse output (begin and stop programmable), e.g. for TDA8708A (ADC) line-locked system clock input signal (27 MHz) +5 V supply input 3 hor. sync pulse reference output (begin and stop programmable), e.g. for gain adj.TDA8708A (ADC) vertical sync output signal (Fig.11) horizontal sync output signal (Fig.16; start point programmable) real time control output; serial increments of HPLL and FSCPLL and status PAL or SECAM sequence (Fig.10) 24.576 MHz clock output (open-circuit for use with external oscillator) 24.576 MHz connection for crystal or external oscillator (TTL compatible squarewave) analog ground line frequency control output signal, multiple of horizontal frequency (nominal 6.75 MHz) +5 V supply input for analog part ground 2 (0 V) 4
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SYMBOL ODD SDA SCL HREF IICSA CPI Y7 Y6 Y5 Y4 Y3 Y2 VSS3 VDD4 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 GPSW0 FEIN MUXC FSO VSS4 FSI PIN 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 port output for general purpose (programmable by subaddress 0D) UV signal output bits UV7 to UV0, part of the digital YUV-bus ground 3 (0 V) +5 V supply input 4 Y signal output bits Y1 to Y0 (luminance), part of the digital YUV-bus Y signal output bits Y7 to Y2 (luminance), part of the digital YUV-bus DESCRIPTION odd/even field identification output (odd = HIGH) I2C-bus data line I2C-bus clock line horizontal reference for YUV data outputs (for active line 720Y samples long) set module address input of I2C-bus (LOW = 1000 101X; HIGH = 1000 111X) clamping pulse input (digital clamping of external UV signals)
SAA7151B
fast enable input (active-LOW to control fast switching due to YUV data; HIGH = YUV high-Z multiplexer control output; source select signal for external ADC (UV signal multiplexing) fast switch and sync insertion output; gated FS signal from FSI or sync insertion pulse in full screen RGB mode ground 4 (0 V) fast switch input signal fed from SCART/peri-TV connector (indicates fast insertion of RGB signals)
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Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SAA7151B
65 MUXC
RESN
CREF
CUV3
CUV2
CUV1
CUV0
VDD1
67 VSS4
handbook, full pagewidth
63 GPSW0
64 FEIN
66 FSO
62 UV0
CUV4 10 CUV5 11 CUV6 12 CUV7 13 CVBS0 14 CVBS1 15 CVBS2 16 CVBS3 17 VDD2 18 VSS1 19 CVBS4 20 CVBS5 21 CVBS6 22 CVBS7 23 GPSW1 24 GPSW2 25 HCL 26
61 UV1
68 FSI
AP 2
9
8
7
6
5
4
3
1
SP
60 UV2 59 UV3 58 UV4 57 UV5 56 UV6 55 UV7 54 Y0 53 Y1
SAA7151A SAA7151B
52 VDD4 51 VSS3 50 Y2 49 Y3 48 Y4 47 Y5 46 Y6 45 Y7 44 CPI
LL27 27
VDD3 28
HSY 29
VS 30
HS 31
SYIS 32
XTAL 33
XTALI 34
VSSA 35
LFCO 36
VDDA 37
VSS2 38
ODD 39
SDA 40
SCL 41
HREF 42
IICSA 43
MEH293
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION System configuration The SAA7151B system processes digital TV signals with line-locked clock in PAL, SECAM and NTSC standards (CVBS or S-Video) as well as RGB signals coming from a SCART/peri-TV connector. The different source signals are switched, if necessary matrixed and converted (Fig.3 and Table 1). 8-bit CVBS data (digitized composite video) and 8-bit UV data (digitized chrominance and /or time-multiplexed colour-difference signals) are fed to the SAA7151B. The data rate is 27 MHz.
Chrominance processing The 8-bit chrominance input signal (signal "C" out of CVBS or Y/C in Fig.4) is fed via the input interface to a bandpass filter for eliminating the DC component, then to the quadrature demodulator. Subcarrier signals from the local oscillator (DTO1) with 90 degree phase shift are applied to its multiplier inputs. The frequency depends on set TV standard.
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Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
handbook, full pagewidth
SAA7151B
+
AO ADI V2
TDA8709A
8-bit ADC and multiplexer (CHROMINANCE) DO(7-0) CLK
CUV(7-0)
U/V
S0 S1 FE CLS CLP +5 V MUXC
HCT4053
C BP R SCART (PERI-TV) G B sync FS SW1 FS* CPI SW2 I 2C-bus (select) CVBS/Y HCL sync AO FSO C R G B sync LP U V CSO CPO GPSW1 LP MULTIPLEXER
TDA8446
VIDEO SWITCH AND MATRIX
clamping
CPI
from SCART interface SAA7151B FSI
CVBS
Y C Y/C Y VIDEO SWITCH V0 CVBS/Y/sync
8-bit ADC (LUMINANCE)
GA GB
DO(7-0)
TDA8540
chroma
LP
ADI
TDA8708A
CVBS(7-0)
CLK GPSW2 GPSW1
MEH305-3
* fast switching of Y signal for insertion
(UV are switched inside SAA7151B)
Fig.3 System configuration, RGB fast switch interface included (SCART).
The multipliers operate as a quadrature demodulator for all PAL and NTSC signals; it operates as a frequency down-mixer for SECAM signals. The two multiplier output signals are converted to a serial UV data stream and applied to two low-pass filter stages, then to a gain controlled amplifier. A final multiplexed low-pass filter achieves, together with the preceding stages, the required bandwidth performance. The from PAL and NTSC originated signals are applied to a comb-filter. The signals, originated from SECAM, are fed through a cloche filter (0 Hz centre frequency), a phase demodulator and a differentiator to obtain frequency-demodulated colour-difference signals. The SECAM signals are fed after de-emphasis to a cross-over switch, to provide the both serial-transmitted colour-difference signals. These signals are finally fed via April 1993 7
the fast switch to the output formatter stages and to the output interface. Chrominance signals are output in parallel (4:2:2) on the YUV-bus. The data rate of Y signal (pixel rate) is 13.5 MHz. UV signals have a data rate of 13.5 MHz/2 for the 4:2.2 format (Table 2) respectively 13.5 MHz/4 for the 4:1.1 format (Table 3). Component processing and SCART interface control The 8-bit multiplexed colour-difference input signal (signal CUV, Fig.1, out of matrixed RGB in Fig.3) is fed via the input interface to a chrominance stop filter (UV signal only can pass through; Figures 22 to 24). Here it is clamped and fed to the offset compensation which can be enabled or disabled via the I2C-bus.
to and from SAA7151B
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
For matrixed RGB signals - the full screen SCART mode and the fast insertion mode (blanking/switching) are selectable. The chrominance stop filter is automatically bypassed in full screen SCART mode. Full screen RGB mode (SCART): The CUV digital input signal (7-0) consists of time-multiplexed samples for U and V. An offset correction for both signals is applied to correct external clamping
SAA7151B
errors. An internal timing correction compensates for slight differences in timing during sampling. The U and V signals are delay-compensated and fed to the output formatter. The format 4:2:2 or 4:1:1 is generated by a switchable filter. The control signals for the front end (Figures 3 and 20) MUXC, status bits FSST1, FSST0 (outputs GPSW2, GPSW1) and FSO are generated by the SAA7151B.
Table 1 MODE
SCART interface control (Fig.3) chroma TDA8709A output of selected CUV FSO GPSW 2 GPSW 1 MUXC TDA8446 input (7-0) to TDA8709A 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C VIN2 high-Z VIN2 U/V high-Z VIN2 U/V CONNECTION luminance fast switch TDA8446 sync (RGB) input selector (via I2C-bus) TDA8540 sync (RGB) Y (Y/C) or CVBS
RGB only Y/C or CVBS only Fast switch
C
VIN1
C
Y (Y/C) or CVBS
C
VIN2
0.5(C+U)/ Y (Y/C) or Y (Y/C) or CVBS 0.5(C+V) CVBS not used Y (RGB) not used 0.5(C+U)/ Y (RGB) 0.5(C+V) not used Y (Y/C) or CVBS sync (RGB)
RGB only
1 1 1 1
Fast switch
1 1 1 1
Fast insertion mode: Fast insertion is applied by FSI pulse to ensure correct timing. The RGB source signal is matrixed into UV and inserted into the CVBS or Y/C source signal after two field periods if FSI pulses are received. The output FSO is set to HIGH during a determined insertion window (screen plain minus 6 % of horizontal and vertical deflection). Switch over depends on the phase of FSI in relation to the valid pixel sequence depending on the phase-different weighting factors. They are applied to the original and the
inserted UV data (Figures 6 and 7) The control signals for the front end (Table 1) MUXC, FSO, status bits FSST1 and FSST0 (outputs GPSW2 and GPSW1) are generated by the SAA7151B. The amplitude of chrominance and colour-difference signals are scaled down by factor 2 to avoid overloading of the chrominance analog-to-digital converter. The amplitudes are reduced in the TDA8446 by signals on lines GPSW2 and GPSW1.
April 1993
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Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
Luminance processing The luminance input signal, a digital CVBS format or an 8-bit luminance format (S-Video), is fed through a sample rate converter to reduce the data rate to 13.5 MHz (Fig.5). Sample rate is converted by means of a switchable pre-filter. High frequency components are emphasized to compensate for loss in the following chrominance trap filter. This chrominance trap filter (fo = 4.43 MHz or fo = 3.58 MHz centre frequency selectable) eliminates the most of the colour carrier signal, therefore, it must be bypassed for S-Video signals. The high frequency components of the luminance signal can be "peaked" in two bandpass filters with selectable transfer characteristic. A coring circuit (1 LSB) can improve the signal, this signal is then added to the original signal. A switchable amplifier achieves a common DC amplification, because the DC gains are different in both chrominance trap modes. Additionally, a cut-off sync pulse is generated for the original signal in both modes. Synchronization The luminance output signal is fed to the synchronization stage. Its bandwidth is reduced to 1 MHz in a low-pass filter (sync pre-filter). The sync pulses are sliced and fed to the phase detectors to be compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. There are three groups of output timing signals: a. signals related to data output signals (HREF) b. signals related to the input signals (HSY, and HCL) c. signals related to the internal sync phase All horizontal timings are derived from the main counter, which represents the internal sync phase. The HREF signal only with its critical timing is phase-compensated in relationship to the data output signal. Future circuit improvements could slightly influence the processing
SAA7151B
delays of some internal stages to achieve a changed timing due to the timing groups b and c. The HREF signal only controls the data multiplexer phase and the data output signals. All timings of the following diagrams are measured with nominal input signals, for example coming from a pattern generator. Processing delay times are taken between input and data output, respectively between internal sync reference (main counter = 0) and the rising edge of HREF. Line locked clock frequency LFCO is required in an external PLL (SAA7157) to generate the line-locked clock frequency LL27 and CREF. YUV-bus, digital outputs The 16-bit YUV-bus transfers digital data from the output interfaces to a feature box, or to the digital-to-analog converter (DAC). Outputs are controlled via the I2C-bus in normal selections, or they are controlled by output enable chain (FEIN, pin 64). The YUV-bus data rate 13.5 MHz. Timing is achieved by marking each second positive rising edge of the clock LL27 synchronized by CREF. YUV-bus formats 4 : 2 : 2 and 4 : 1 : 1 The output signals Y7 to Y0 are the bits of the digital luminance signal. The output signals UV7 to UV0 are the bits of the digital colour-difference signal. The frames in the Tables 2 and 3 are the time to transfer a full set of samples. In case of 4 : 2 : 2 format two luminance samples are transmitted in comparison to one U and one V sample within one frame. The time frames are controlled by the HREF signal, which determines the correct UV data phase. The YUV data outputs can be enabled or set to 3-state position by means of the FEIN signal. FEIN = LOW enables the output; HIGH on this pin forces the Y and U/V outputs to a high-impedance state (Fig.6).
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April 1993
handbook, full pagewidth
clamping
CPI UV (7-0) OFTS, IPBP DELAY COMPENSATION CGFX, AMPF(3-0) TIME INTERPOLATION UV FAST SWITCH AND WEIGHTING
44 UV
Philips Semiconductors
OSCE
CHROMINANCE STOP FILTER, OFFSET COMPENSATION
CVBS (7-0) C QUADRATURE DEMODULATOR UV LOWPASS FILTER GAIN CONTROLLED AMPLIFIER LOWPASS FILTER COMB FILTER AND SECAM RECOMBINATION
CUV (7-0)
INPUT INTERFACE
CHROMINANCE BANDPASS
42 HREF OUTPUT FORMATTER AND OUTPUT 64 FEIN INTERFACE Y (7-0)
FISE UV CKTS (4-0) CHCV (7-0) CKTO (4-0) LFIS (2-1) LOOP FILTER PI2 CLOCHE FILTER (SECAM) OFTS COLO OEDY OEDC OEHS CHSB
COFF
BYPS YDEL0 CDMO DISCRETE TIME OSCILLATOR (DTO1) AND DIVIDER
CHRS UVSS CDPO
HUEC(7-0)
CCIR SUVI
RTCO 32 LOOP FILTER PI1
24 GPSW2 25 GPSW1
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
10
BURST GATE ACCUMULATOR SEQUENCE PROCESSOR PHASE DEMODULATOR AND AMPLITUDE DETECTOR DIFFERENTIATOR PLSE(7-0) SEQA SESE(7-0) CDVI CSTD(2-0) ASTD CDET SXCR STANDARD DETECTION DE-EMPHASIS
SAA7151B
SCART INTERFACE CONTROL
65 MUXC 66 FSO 68 FSI
FSST
CHROMINANCE
FSAU FSDL(2-0) GPSI(2-1) OFTS FSIV
to luminance
from luminance
MEH294
Product specification
SAA7151B
Fig.4 Detailed block diagram; continued in Fig.5.
handbook, full pagewidth
April 1993
to output interface CHROMINANCE TRAP CORING VARIABLE DELAY COMPENSATION VARIABLE BANDPASS FILTER WEIGHTING AND ADDING STAGE BYPS BPSS (1-0) MATCHING AMPLIFIER PREF BYPS CORI APER (1-0) YDEL (3-1)
Philips Semiconductors
from input interface
SAMPLE RATE CONVERTER
PRE-FILTER
PREF
OFFSET COMPENSATION
LUMINANCE
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
11
4 CREF PHASE DETECTOR FINE PHASE DETECTOR COARSE LOOP FILTER PROGRAMMABLE DELAY LINE-LOCKED CLOCK GENERATOR 27 LL27 VTRC HLCK HLCK HPLL 33 XTAL DISCRETE TIME OSCILLATOR (DTO2) CRYSTAL CLOCK GENERATOR 34 XTALI SCEN OEVS OEHS HCLB (7-0) HCLS (7-0) HSYB (7-0) HSYS (7-0) HPHI (7-0) IDEL (7-0)
PRE-FILTER SYNC
SYNC SLICER
SAA7151B SYNC
SCL HLCK COUNTER VERTICAL PROCESSOR
41
SDA
40
I2C-BUS CONTROL
VNOI (1-0) WIND BOFL BFON FSEL AUFD FIDT
DAC
IICSA 26 HCL HSY VS HS 29 30 31
43 39 ODD
63
36
MEH295
GPSW0
LFCO
Product specification
SAA7151B
Fig.5 Detailed block diagram; continued from Fig.4.
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
Table 2
SAA7151B
for the 4 : 2 : 2 format (720 pixels per line). The quoted frequencies are valid on the YUV-bus. The time frames are controlled by the HREF signal. OUTPUT PIXEL BYTE SEQUENCE Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U0 U1 U2 U3 U4 U5 U6 U7 0 0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 V0 V1 V2 V3 V4 V5 V6 V7 1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U0 U1 U2 U3 U4 U5 U6 U7 2 2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 V0 V1 V2 V3 V4 V5 V6 V7 3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U0 U1 U2 U3 U4 U5 U6 U7 4 4 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 V0 V1 V2 V3 V4 V5 V6 V7 5
Y0 (LSB) Y1 Y2 Y3 Y4 Y5 Y6 Y7 (MSB) UV0 (LSB) UV1 UV2 UV3 UV4 UV5 UV6 UV7 (MSB) Y frame UV frame Table 3
for the 4 : 1 : 1 format (720 pixels per line). The quoted frequencies are valid on the YUV-bus. The time frames are controlled by the HREF signal. OUTPUT PIXEL BYTE SEQUENCE Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V6 V7 U6 U7 0 0 12 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V4 V5 U4 U5 1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V2 V3 U2 U3 2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V0 V1 U0 U1 3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V6 V7 U6 U7 4 4 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V4 V5 U4 U5 5 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V2 V3 U2 U3 6 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 V0 V1 U0 U1 7
Y0 (LSB) Y1 Y2 Y3 Y4 Y5 Y6 Y7 (MSB) UV0 (LSB) UV1 UV2 UV3 UV4 UV5 UV6 UV7 (MSB) Y frame UV frame April 1993
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
Signal levels (Figures 12, 13 and 14)
SAA7151B
The nominal input and output signal levels are defined by a colour bar signal with 75 % colour, 100 % saturation and 100 % luminance amplitude (EBU colour bar). CUV-bus input format The CUV-bus transfers the digital chrominance/colour-difference signals from the ADC to the SAA7151B (Fig.6; Table 1): * normal mode for digital chrominance transmission. * UV colour-difference mode for colour-difference signals UV (out of matrixed RGB signals) * FS mode (fast switch mode; UV inserted into chrominance signal C with addition of the two signal spectra). RTCO output The RTCO output signal (Fig.10) contains serialized information about actual clock frequency, subcarrier frequency and PAL/SECAM sequence. This signal may preferably be used with the frequency-locked digital video encoder SAA7199B.
handbook, full pagewidth LL27
to 3-state CREF
from 3-state
HREF tSU tHD
FEIN tOH YUV
MEH548
tOS
Fig.6 Timing example of fast enable input (FEIN).
April 1993
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Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SAA7151B
handbook, full pagewidth LL27 clock
0
1
2
3
4
5
LL13.5 clock
0
1
2
MUXC Normal mode (chrominance pixel byte sequence) chrominance C0 C1 C2 C3 C4 C5
UV colour-difference mode (UV pixel byte sequence) colourdifference V0 V1
(1)
U2
U3
(1)
V4
V5
(1)
valid colourdifference
U0
V1
U3
V5
Fast switch mode (data insertion) CUV (V0 + C0)/2 (V1 + C1)/2
(1)
(U2 + C2)/2
(U3 + C3)/2
(1)
(V4 + C0)/2
(V5 + C5)/2
(1)
valid CUV
(V1 + C1)/2
(U3 + C3)/2
(V5 + C5)/2
MEH332
Fig.7
CUV input formats. (1) each second sample only after a MUXC change is taken for down-sampling to 13.5 MHz to reduce cross-talk components between U and V signals.
April 1993
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Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SAA7151B
handbook, full pagewidth
new
0 old + 1 new 1/8 old + 7/8 new 1/4 old + 3/4 new 3/8 old + 5/8 new 1/2 old + 1/2 new 5/8 old + 3/8 new 3/4 old + 1/4 new 7/8 old + 1/8 new
old
Note: in 4:2:2 format weighting in 1/4 steps only.
T(n-2)
T(n-1)
T(n)
T(n+1)
T(n+2)
MEH307
Fig.8 Addition of weighted components.
handbook, full pagewidth
FS
1 3/4 1/2 1/4
fast switch weighting for 4:2:2 format
UV LL6.75 LL27 0 0
U0, V0 1 1 2 3 4
U1, V1 2 5 6 7 8
U2, V2 3 9
U3, V3 4
10 11 12 13 14 15 16
FS
1
7/8 3/4 5/8 1/2 3/8 1/4 1/8
fast switch weighting for 4:1:1 format
UV LL3.375 LL27 0 0 1 2
U0, V0 1 3 4 5 6 7 8 9
U1, V1 3 10 11 12 13 14 15 16
MEH308
Fig.9 Weighting factors of fast switching for 4:2:2 and 4:1:1 formats.
April 1993
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Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SAA7151B
handbook, full pagewidth LL27
CREF
HREF start of active line Byte number for pixels: Y signal 50/60 Hz U and V signal U0 V0 U2 V2 U4 V4 U6 V6
MEH297
0
1
2
3
4
5
6
7
handbook, full pagewidth LL27
CREF
HREF
end of active line
Byte number for pixels: Y signal 50/60 Hz U and V signal U714 V714 U716 V716 U718 V718
MEH298
714
715
716
717
718
719
Fig.10 Line control by HREF in 4:2:2 format for 50 Hz and 60 Hz systems.
handbook, full pagewidth
H/L transition (counter start) 128 clocks 13
HPLL increment bits 13 to 0 0
4 bits reserve
bit 21 20
FSCPLL increment bits 21 to 0 15 10 5
5 bits reserve sequence bit(1) reserved(2) 10
RTCO 0
(1) Sequence bit:
4
8
14
19 time slot (LL27/4) valid not valid
61
67
MEH341
SECAM: 0 equals DB-line 1 equals DR-line PAL: 0 equals (R-Y) line normal 1 equals (R-Y) line inverted NTSC: 0 (no change) (2) Reserve bits: 236 for 50 Hz systems; 233 for 60 Hz systems
Fig.11 RTCO timing.
April 1993
16
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
Condition: handbook, full pagewidth Nominal input signal, 50 Hz (a) 1st field 625 1 2 3 4 5 6 7 8
SAA7151B
9
input CVBS
HREF 503 x 2/LL27 VS 2 x 2/LL27
ODD
(b) 2nd field 313 314 315 316 317 318 319 320 321
input CVBS
HREF 71 x 2/LL27 VS
ODD
2 x 2/LL27
MEH335
Fig.12 Vertical timing diagram at 50 Hz.
April 1993
17
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
Condition: handbook, full pagewidth Nominal input signal, 60 Hz (a) 1st field 525 1 2 3 4 5 6 7 8
SAA7151B
9
input CVBS
HREF 491 x 2/LL27 VS 2 x 2/LL27
ODD
(b) 2nd field 263 264 265 266 267 268 269 270 271
input CVBS
HREF 59 x 2/LL27 VS
ODD
2 x 2/LL27
MEH336
Fig.13 Vertical timing diagram at 60 Hz.
April 1993
18
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
handbook, +127 full pagewidth
SAA7151B
+127 reserved +105 +100 +76
+106 +95
luminance 60 Hz mode luminance 50 Hz mode 0 chrominance 60 Hz mode chrominance 50 Hz mode 0 V U component of colour-difference signal -52 -64 blanking level -76 -91 -103 -128 -132 C chrominance
sync clipped
-91 -103 -128 (b) CUV input signal range (U and V out of RGB; in FS mode ranges x 0.5).
(a) CVBS input signal range.
+255 +235 white 100%
+127 +100
+127 +105
blue 75%
red 75%
luminance signal output range +128 0 U-component output signal range 0 V-component output signal range
-101 +16 0 (c) Y output signal range. black -128
yellow 75%
-106 -128
cyan 75%
(d) U output signal range (B-Y).
(e) V output signal range (R-Y).
MEH299
Notes: 1. All levels related to EBU colour bar. 2. Values in decimal at 100% luminance and 75% chrominance amplitude
Fig.14 Input and output signal ranges in DTV mode (digital TV).
April 1993
19
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
handbook, +127 full pagewidth
SAA7151B
+127 reserved 100% white +84 +76
+106 +95
luminance 60 Hz mode luminance 50 Hz mode 0 chrominance 60 Hz mode chrominance 50 Hz mode 0 V U component of colour-difference signal C chrominance
-52 -64
blanking level -76 -84
-91 -103 -128 -132
sync clipped -128 (b) CUV input signal range (U and V out of RGB; in FS mode ranges x 0.5).
(a) CVBS input signal range.
+255 +235 white 100%
+255 +212
+255 +212
blue 75%
red 75%
luminance signal output range +128 +128 U-component output signal range +128 V-component output signal range
+44 +16 0 (c) Y output signal range. black 0
yellow 75%
+44
cyan 75%
0 (d) U output signal range (B-Y). (e) V output signal range (R-Y).
MEH300
Notes: 1. All levels are related to EBU colour bar. 2. Values in decimal at 100 % luminance and 75 % chrominance amplitude. 3. For SECAM input signals the CCIR levels will be exceeded.
Fig.15 Input and output signal ranges in CCIR mode.
April 1993
20
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SAA7151B
handbook, full pagewidth
63 x 2/LL27 burst
CVBS
HSY step size 2/LL27 HSY +191 programming range (step size: 2/LLC) HCL -64 0
HCL +127 programming range (step size: 2/LL27) +235 Y-output +16 0 Yout
0 83.5 x 2/LL27(1) 4 x 2/LL27 (50 HZ) 10 x 2/LL27 (60 HZ) HREF position
-128
HREF 720 x 2/LL27
...719 144 x 2/LL27 (50 HZ) 138 x 2/LL27 (60 HZ) HREF length fix 16 x 2/LL27 (50 HZ) 12 x 2/LL27 (60 HZ)
0...
HS HS programming range (step size: 8/LL27) +431 0
MEH549
64 x 2/LL27
-432
(1) the processing delay will be influenced in future enhancements. (1) the processing delay will be ifluenced in future enhancements
Fig.16 Horizontal sync and clamping timing for 50/60 Hz (signals HSY, HCL, HREF and HS).
April 1993
21
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SAA7151B
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); ground pins 19, 35, 38, 51 and 67 as well as supply pins 5, 18, 28, 37 and 52 connected together. SYMBOL VDD Vdiff GND VI VO Ptot Tstg Tamb VESD Note 1. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor; inputs and outputs are protected against electrostatic discharge in normal handling. Normal precautions appropriate to handle MOS devices is recommended ("Handling MOS Devices"). PARAMETER supply voltage (pins 5, 18, 28, 37, 52) difference voltage VSS A - VSS(1 to 4) voltage on all inputs voltage on all outputs (IO max = 20 mA) total power dissipation storage temperature range operating ambient temperature range electrostatic handling(1) for all pins - -0.5 -0.5 - -65 0 - MIN. -0.5 7.0 100 VDD+0.5 VDD+0.5 2.5 150 70 2000 MAX. V mV V V W C C V UNIT
April 1993
22
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = 0 to 70 C unless otherwise specified. SYMBOL VDD IDD I2C-bus, VI L VI H I40, 41 IACK VO L VI L VI H VI L VI H Ileak CI input leakage current input capacitance data inputs; note 1 I/O high-impedance clock inputs tSU.DAT tHD.DAT VO L VO H CL Vo V36 VO L VO H CL input data set-up time input data hold time Fig.17 other input voltages PARAMETER supply voltage range (pins 5, 18, 28, 37, 52) total supply current (pins 5, 18, 28, 37, 52) SDA and SCL (pins 40 and 41) input voltage LOW input voltage HIGH input current output current on pin 40 output voltage at acknowledge acknowledge I40 = 3 mA LOW HIGH LOW HIGH -0.5 3 - 3 - -0.5 2.4 -0.5 2.0 - - - - 11 3 - - - - - - - - - - - - - - - - - - - - - - - CONDITIONS MIN. 4.5 VDD = 5 V; inputs LOW; outputs not connected - 5 100 TYP.
SAA7151B
MAX. 5.5 250
UNIT V mA
1.5 VDD+0.5 10 - 0.4
V V A mA V
Data, clock and control inputs (pins 3, 4, 6 to 17, 20 to 23, 27, 34, 64 and 68); Figures 14 and 15 LL27 input voltage (pin 27) 0.6 VDD+0.5 0.8 VDD+0.5 10 8 8 10 - - V V V V A pF pF pF ns ns
YUV-bus, HREF and VS outputs (pins 30, 42, 45 to 50 and pins 53 to 62), Figures 10, 14 and 15 output voltage LOW output voltage HIGH load capacitor notes 1 and 2 0 2.4 15 0.6 VDD 50 V V pF
LFCO output (pin 36) output signal (peak-to-peak value) output voltage range note 2 1.4 1 2.6 VDD 0.6 VDD 25 V V
Control outputs (pins 24 to 26, 29, 31, 32, 33, 39, 63, 65 and 66); Figures 12, 16 and 17 output voltage LOW output voltage HIGH load capacitor notes 1 and 2 0 2.4 7.5 V V pF
April 1993
23
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SYMBOL PARAMETER CONDITIONS Figures 10, 12 and 13 YUV, HREF, VS at CL = 15 pF; controls at CL = 7.5 pF tOS output set-up time YUV, HREF, VS at CL = 50 pF; controls at CL = 25 pF tSZ tZS fC fn f / fn X1 data output disable transition time data output enable transition time to 3-state condition from 3-state condition 13 13 20 20 22 20 400 Figures 19 and 20; note 3 3rd harmonic - - - 0 8 - - - Fig.9 and 17 note 4 tLL27H /t LL27 35 40 - - - 50 - - 24.576 - - - - 40 - - - - - - - MIN. TYP.
SAA7151B
MAX.
UNIT
Timing of YUV-bus and control outputs tOH output signal hold time
- - - - - - - - 50 20 70 - 80 - -
ns ns ns ns ns ns
Chrominance PLL catching range Hz
Crystal oscillator nominal frequency permissible deviation fn temperature deviation from fn crystal specification: temperature range Tamb load capacitance CL series resonance resistance RS motional capacitance C1 parallel capacitance C0 Line locked clock input LL27 (pin 27) tLL27 tp tr tf Notes cycle time duty factor rise time fall time
MHz 10-6 10-6 C pF fF pF
1.520% 3.520%
39 60 5 6
ns % ns ns
1. Data output signals are Y7 to Y0 and UV7 to UV0. All other are control signals. 2. Levels are measured with load circuit. YUV-bus, HREF and VS outputs with 1.2 k in parallel to 50 pF at 3 V (TTL load); LFCO output with 10 k in parallel to 15 pF and other outputs with 1.2 k in parallel to 25 pF at 3 V (TTL load). 3. Recommended crystal: Philips 4322 143 05291. 4. tSU, tHD, tOH and tOD include tr and tf.
April 1993
24
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
Table 4 OEDY 0 0 1 1 X High-impedance control for YUV-bus (Fig.17) OEDC 0 1 0 1 X FEIN 0 0 0 0 1 Y(7:0) Z Z active Z Z UV(7:0) Z active Z Z Z
SAA7151B
handbook, full pagewidth
tLL27 tLL27H 2.4 V
clock input LL27
1.5 V 0.6 V tSU tHD not valid 2.0 V tf tr
input data 0.8 V
2.0 V input CREF 0.8 V tZS tOH tOS not valid 2.4 V output data 0.6 V tSZ tSU tHD 2.4 V input FEIN 0.6 V
MEH550
tSU tHD
Fig.17 Data input and output timing diagram.
April 1993
25
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SAA7151B
handbook, full pagewidth
24.576 MHz (3rd harmonic)
XTAL 10 pF
33 SAA7151B
XTAL
33 SAA7151B
X1 XTALI 1 nF 10 H (20%) 10 pF 34
XTALI
34
MEH302
(a)
(b)
Fig.18 Oscillator application (a) and optional clock from external (b).
April 1993
26
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SAA7151B
handbook, full pagewidth
CPI VSS 67 51 38 19 44 UV0 UV1 UV2 UV3 UV4 UV5 UV6 UV7 YUV-bus
0.1 F 0.1 F 0.1 F 0.1 F digital +5 V chrominance CUV7 to CUV0 VDD CUV0 CUV1 CUV2 CUV3 CUV4 CUV5 CUV6 CUV7 luminance CVBS7 to CVBS0 L0 L1 L2 L3 L4 L5 L6 X1 : Philips 4322 143 05291 X1 L7
5 18 28 52
62 61 60 59 58 57 56 55
UV7 to UV0
6 7 8 9 10 11 12 13 14 15 16 17 20 21 22 23 33 42 41 40 34 39 63 64 HREF SCL SDA ODD GPSW0 FEIN IICSA I2C-bus 54 53 50 49 48 47 46 45 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 RTCO HS VS HSY HCL Y7 to Y0
SAA7151B
32 31 30 29 26
24.576 MHz
12 pF
10 H 1 nF
12 pF RESN
43 2 3 27 1 35 24 25 36 65 66 68 37 VSSA VDDA
(from SCART) FS digital 680 150 BAT45 pF
digital
4
MUXC FSO
LFCO
FSI +5 V 2.2 H 0.1 F f > 13 MHz
680
75
11 19 GPSW1 GPSW2 RESN LL27A CREF LL27B LL13A LL13B 12 7 15 10 14 20 16
5 2 3 4 8
0.1 F 10 F 0.1 F
VDD analog
+5 V
analog VDD digital +5 V
SAA7157
17 1 6 9 13 18 digital
MEH328
0.1 F
0.1 F
Fig.19 Application of SAA7151B.
April 1993
27
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SAA7151B
handbook, full pagewidth
+12 V
2.2 H 22 F 4.7 k 1 2 1 nF 4.7 F 3 4 0.1 F 5 0.1 F 6 0.1 F 7 8 14 13 CVBS/Y 0.1 F 9 0.1 F chrominance bandpass filter C 10 12 11 C signal HCL GPSW1 CLO 47 k 1 k GPSW2 FSO from / to TDA8708/09 +5 V TDA8446 15 V signal 16 Y signal 18 17 VP 75 75 20 0.15 F 19 0.1 F +12 V sync
sync
from SCART connector
U signal
B G R
75 75
FS
to SAA7151B
SCL SDA
I2C-bus
SCL SDA (to SAA7151B) 75 1 unused signal outputs 2 3 4 5 0.1 F 6 TDA8540 15 14 13 12 11 0.1 F C 22 VP +8 V 10 F 1.6 k 22 0.1 F 220 pF 330
MEH330
10 k 20 10 k 19 18 17 16 22 F 150 7808 stabilizer 150 audio source control
22 F 75 C (chrominance) 75 CVBS 0.1 F
7 8
75 Y
9 0.1 F 10
Fig.20 Application of input signal selecting (SCART interface).
April 1993
28
from/to TDA8446
10 0.1 F digital 23 0.22 F 24 VDDO 25 6.2 k 26 analog 27 22 3 k 28 5.6 5.6 120 1 k 1 3 2 VDDD CLK CVBS4 CVBS3 CVBS2 CVBS7 68 pF 0.1 F 0.1 F 4 0.1 F 5 6 9 8 TDA8708A 7 6 5 4 3 2 1
VDDD CLK CUV4 CUV5 CUV6 CUV7 22 120 0.1 F
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
29
20 21 22 23 24 25 26 27 28 5.6
2.2 k
1 F
VDDA
(+5 V)
5 MHz low-pass filter
0.1 F
0.22 F
5.6
10 F
HCL to pin 9 of TDA8446
CPI CVBS(7-0)
10
CLO from pin 4 of TDA8446
analog HCL
LL27A
+5 V (analog supply)
+5 V (digital supply)
MEH329
HSY
UV gain level for CCIR
Product specification
SAA7151B
Fig.21 Application circuit analog-to-digital conversions.
from/to SAA7151B
April 1993
GPSW1 GPSW2 NOR MUXC 33 pF 1 k VDDA BC547 6.8 k 220 14 12 4.7 F 10 F 15 1 F 1.5 k 16 17 18 19 1 mH 20 3.3 k 21 VDDA 22 7 TDA8709A VDDO 8 1 F 68 pF 0.1 F 9 10 CUV3 digital 11 CUV2 12 CUV1 13 1 F VIN1 VIN2 15 1.2 k VIN0 16 13 12 11 CVBS3 CVBS2 CVBS1 17 18 19 VIN1 VIN2 CVBS0 14 VIN0 CUV0 CUV(7-0) 14 BC547 220 1 nF 1.5 k 10 F 100 k 3 5 6, 8, 10 7 4 2 4.7 k F 1 nF 0.1 F HCT4053 13 11 16 9
to pin 8
handbook, full pagewidth
V signal from pin 15
1 k
Philips Semiconductors
2 MHz low-pass filters
2 k
U signal from pin 17
1 k
2 k
C signal from pin 11
Y or CVBS from pin 16
4.7 F
1 F
1 F
680
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
I2C-BUS FORMAT S S SLAVE ADDRESS A SUBADDRESS(1) DATA P X SLAVE ADDRESS = = = = = = = A SUBADDRESS A DATA0 A
SAA7151B
DATAn
A
P
start condition 1000 101X (IICSA = LOW) or 1000 111X (IICSA = HIGH) acknowledge, generated by the slave subaddress byte (Table 5) data byte (Table 5) stop condition read/write control bit X = 0, order to write (the circuit is slave receiver) X = 1, order to read (the circuit is slave transmitter)
Note 1. If more than 1 byte DATA are transmitted, then auto-increment of the subaddress is performed. Remarks: - Prior to reset of the IC all outputs are undefined. - After power-on reset, the control register 12 (hex) is set to 00 (hex).
April 1993
30
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
Table 5
SAA7151B
I2C-bus; DATA for status byte (X in address byte = 1; slave address 8B (hex) at IICSA = LOW or 8F (hex) at IICSA = HIGH) DATA D7 D6 D5 D4 FSST1 D3 D2 D1 CDET1 D0 CDET0
FUNCTION
status byte Function of the bits: STTC HLCK FIDT FSST1 to FSST0
STTC HLCK FIDT
FSST0 CDET2
Status time constant (to be used for gogical combfilter SAA7152) 0 = TV mode; 1 = VCR mode Horizontal PLL information: Field information Fast switching output mode: 0 = HPLL locked; 1 = HPLL unlocked 0 = 50 Hz system detected; 1 = 60 Hz system detected FSST1 0 0 1 1 FSST0 0 1 0 1 CDET2 0 0 1 1 0 0 1 1 mode RGB; FSI = HIGH (pin 68) Y/C; FSI = LOW (pin 68) fast switching (toggle) not used CDET2 standard 0 1 0 1 0 1 0 1 PAL-B/G, -H, -I; 50 Hz PAL-N; 50 Hz SECAM; 50 Hz PAL-M; 60 Hz PAL 4.43; 60 Hz NTSC-M; 60 Hz NTSC 4.43; 60 Hz black/white
---------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------- CDET2 to CDET0 Identified colour standard CDET2 0 0 0 0 1 1 1 1
April 1993
31
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
Table 6
SAA7151B
I2C-bus; subaddress and data bytes for writing (X in address byte = 0; slave address 8A (hex) at IICSA = LOW or 8E at IICSA = HIGH) data byte subaddress byte D7 D6 IDEL6 HSYB6 HSYS6 HCLB6 HCLS6 HPHI6 PREF HUEC6 CSTD1 LFIS1 PLSE6 SESE6 GPSI2 CHSB COFF FSEL OFTS CHCV6 OEDC D5 IDEL5 HSYB5 HSYS5 HCLB5 HCLS5 HPHI5 BPSS1 HUEC5 CSTD0 LFIS0 PLSE5 SESE5 D4 IDEL4 HSYB4 HSYS4 HCLB4 HCLS4 HPHI4 BPSS0 HUEC4 CKTQ4 CKTS4 PLSE4 SESE4 D3 IDEL3 HSYB3 HSYS3 HCLB3 HCLS3 HPHI3 D2 IDEL2 HSYB2 HSYS2 HCLB2 HCLS2 HPHI2 D1 IDEL1 HSYB1 HSYS1 HCLB1 HCLS1 HPHI1 D0 IDEL0 HSYB0 HSYS0 HCLB0 HCLS0 HPHI0 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 IDEL7 HSYB7 HSYS7 HCLB7 HCLS7 HPHI7 BYPS HUEC7 CSTD2 OSCE PLSE7 SESE7 FSAU COLO CCIR AUFD ASTD CHCV7 OEDY
function increment delay H-sync HSY begin H-sync HSY stop
H-clamp HCL begin H-clamp HCL stop H-sync after PHI1 luminance control hue control miscellaneous controls #1 miscellaneous controls #2 PAL switch sensitivity SECAM switch sensitivity miscellaneous controls #3 miscellaneous controls #4 miscellaneous controls #5 miscellaneous controls #6 miscellaneous controls #7 chroma gain reference miscellaneous controls #8
BFBY CORI HUEC3 HUEC2 CKTQ3 CKTQ2 CKTS3 PLSE3 SESE3 CKTS2 PLSE2 SESE2
APER1 APER0 HUEC1 HUEC0 CKTQ1 CKTQ0 CKTS1 PLSE1 SESE1 CKTS0 PLSE0 SESE0
GPSI1 CGFX GPSW0 SUVI OEHS OEVS HPLL IPBP CHCV5 VNOI1 SCEN CDVI CHCV4 VNOI0
AMPF3 AMPF2 SXCR FSDL2 UVSS CHRS VTRC YDEL3 MUIV YDEL2
AMPF1 AMPF0 FSDL1 FSDL0 CDMO CDPO FSIV YDEL1 WIND YDEL0
CHCV3 CHCV2 BFON BOFL2
CHCV1 CHCV0 BOFL1 BOFL0
April 1993
32
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
Function of the bits of Table 6
SAA7151B
IDEL7 to IDEL0 "00"
Increment delay time, step size = 4/LL27 = 148 ns(1) D7 D6 D5 D4
1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 1 1 1 0 0 0 0 0
D3
1 0 0 1 1 1 0 0
D2 D1 D0 decimal number 1 0 0 0 0 0 1 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 -217 to -256 0 -1 to -110 -111 to -214 -215 -216
note
minimum -148 ns -16.3 s (outside available range) -16.44 s -31.7 s (maximum value at FSEL = 1) -31.85 s (outside central counter range at FSEL = 1 (2)) -32.0 s (maximum value at FSEL = 0 (2)) -32.148 s (outside central counter range at FSEL = 0 (2)) -37.9 s (outside central counter (2))
HSYB7 to HSYB0 HSYS7 to HSYS0 "01" and "02"
Horizontal sync begin, step size = 2/LL27 = 74 ns Horizontal sync stop, step size = 2/LL27 = 74 ns D7 1 0 0 1 1 D6 D5 D4 0 0 0 1 1 1 0 0 1 0 1 0 0 1 0 D3 1 0 0 1 0 D2 D1 1 0 0 1 0 1 0 0 1 0 D0 decimal multiplier 1 1 0 1 0 191 to 1 0 -1 to -64 note -14.2 s (maximum negative value) -74 ns 0 equals reference value +74 ns +4.7 s
HCLB7 to HCLB0 HCLS7 to HCLS0 "03" and "04"
Horizontal clamp begin, step size = 2/LL27 = 74 ns Horizontal clamp stop, step size = 2/LL27 = 74 ns D7 0 0 0 1 1 D6 D5 D4 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 D3 1 0 0 1 0 D3 1 1 1 0 0 1 0 0 0 D2 D1 1 0 0 1 0 1 0 0 1 0 D0 decimal multiplier 1 1 0 1 0 127 to 1 0 note -9.4 s (maximum negative value) -74 ns 0 equals reference value +74 ns +9.5 s (maximum positive value) note ) forbidden (outside available central ) counter range) -32 s (maximum negative value) -0.296 ns 0 equals reference value +0.296 s +31.7 s (maximum positive value) ) forbidden (outside available central ) counter range)
-1 to -128
HPHI7 to HPHI0 "05"
Horizontal sync start, step size = 8/LL27 = 296 ns D7 0 0 0 0 0 1 1 1 1 D6 D5 D4 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 D2 D1 1 1 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 D0 decimal multiplier 1 1 0 1 0 1 1 0 0 +127 to +109 +108 to +1 0 -1 to -107 -108 to -128
April 1993
33
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
BYPS "06" PREF Input mode select bit: 0 = CVBS mode (chroma trap active) 1 = S-Video mode (chroma trap by-passed) 0 = pre-filter bypassed; 1 = pre-filter on
SAA7151B
Use of pre-emphasis (to be used if chrominance trap is active):
----------------- --------------------------------------------------------------------------------------------------------
BPSS1 to BPSS0 Aperture bandpass to select different centre frequencies (Figures 25 to 40): BPSS1 0 0 1 1 BFBY CORI APER1 to APER0 Coring function: Aperture factor (Figures 25 to 40): APER1 0 0 1 1 HUE7 to HUE0 "07" CSTD2 to CSTD0 "08" APER0 0 1 0 1 factor 0 0.25 0.5 1 BPSS0 0 1 0 1 centre frequency 4.1 MHz 3.8 MHz 2.6 MHz 2.9 MHz 0 = bandfilter active; 1 = bandfilter bypassed 0 = coring off; 1 = 1 LSB coring
Bandfilter bypass switching:
Hue control from +178.6 to -180.0, equals data bytes 7F to 80 (hex); 0 equals 00. Forced colour standard of input signal; CSTD2 0 0 0 0 1 1 1 1 CSTD1 0 0 1 1 0 0 1 1 CSTD0 0 1 0 1 0 1 0 1 standard PAL-B/G, -H, -I; 50 Hz PAL-N; 50 Hz SECAM; 50 Hz PAL-M; 60 Hz PAL 4.43; 60 Hz NTSC-M; 60 Hz NTSC 4.43; 60 Hz black/white
----------------- --------------------------------------------------------------------------------------------------
CKTQ4 to CKTQ0 Colour killer threshold QAM (PAL/NTSC): CKTQ4 1 1 0 CKTQ3 1 0 0 CKTQ2 1 0 0 CKTQ1 1 0 0 CKTQ0 1 0 0 approximately -30 to -24 dB -24 dB to -18 dB
April 1993
34
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
OSCE "09" LFIS1 to LFIS0 External UV offset compensation: 0 = disabled; 1 = enabled
SAA7151B
----------------- --------------------------------------------------------------------------------------------------
Chrominance gain control (AGC filter): LFIS1 0 0 1 1 CKTS4 to CKTS0 PLSE7 to PLSE0 "0A" SESE7 to SESE0 "0B" FSAU; GPSI2, and GPSI1 "0C" LFIS0 0 1 0 1 control of loop filter time constant slow medium fast actual gain, stored (for test purposes only)
----------------- --------------------------------------------------------------------------------------------------
Colour killer threshold SECAM as previously described under CKTQ subaddress "08" PAL switch sensitivity from LOW to HIGH (HIGH means immediate sequence correction), equals FF to 00 (hex), MEDIUM equals 80. SECAM switch sensitivity from LOW to HIGH (HIGH means immediate sequence correction), equals FF to 00 (hex), MEDIUM equals 80. Set port outputs (general purpose switching, internal) FSAU 0 0 0 0 1 CGFX AMPF3 to AMPF0 GPSI2 0 0 1 1 X GPSI1 0 1 0 1 X output GPSW2 (pin 25) LOW LOW HIGH HIGH status bit FSST1 set output GPSW1 (pin 24) LOW HIGH LOW HIGH status bit FSST0 set
----------------- --------------------------------------------------------------------------------------------------
Chrominance gain pre-determination: 0 = gain controlled via loop; 1 = gain set by AMPF-bits Chrominance amplification factor AMPF3 AMPF2 AMPF1 AMPF0 gain -6 dB 0 dB +1.5 dB +3 to +16.5 dB (approximately 1.5 dB steps) +17 dB
----------------- --------------------------------------------------------------------------------------------------
0 0 0 1
0 1 1 1
0 0 0 1
0 0 1 1
April 1993
35
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
COLO "0D" CHSB GPSW0 SUVI SXCR FDSL2 to FDSL0 Colour-on bit: Chrominance (UV) output code: General purpose port output (pin 63): SECAM UV output signal polarity: SECAM cross-colour reduction: Fast switching delay adjustment in 37 ns steps: FDSL2 0 0 0 0 1 1 1 1 CCIR "0E" COFF OEHS OEVS UVSS CHRS FDSL1 0 0 1 1 0 0 1 1 FDSL0 0 1 0 1 0 1 0 1 delay 0 37 ns 74 ns 111 ns -148 ns (negative delay) -111 ns -74 ns -37 ns 0 = colour-killer automatically enabled; 1 = forced colour-on.
SAA7151B
0 = two's complement; 1 = straightly binary 0 = LOW; 1 = HIGH 0 = U and V positive; 1 = U and V negative 0 = off; 1 = on
----------------- --------------------------------------------------------------------------------------------------
Set CCIR mode: 0 = digital TV mode (DTV); 1 = CCIR mode Set colour off: 0 = colour on; 1 = colour off Enable horizontal sync outputs HS and HREF: Enable vertical sync output VS: Select UV pixel sample: S-Video input mode: 0 = output high-impedance; 1 = HS and HREF enabled
0 = output high-impedance; 1 = VS enabled 1 = first pixel after U/V signal has changed; 0 = second pixel (free of crosstalk signals) 0 = chrominance signal from CVBS or CUV input and controlled by BYPS (subaddress 06); 1 = S-Video mode; chrominance signal from CUV input CDMO 0 1 0 CDPO 0 X 1 no delay -37 ns (negative delay) +37 ns
----------------- --------------------------------------------------------------------------------------------------
CDMO, CDPO Chrominance delay:
AUFD "0F" FSEL HPLL SCEN
Automatic field detection: Field select (AUFD-bit = 0): Horizontal PLL: Sync and clamping pulse enable:
0 = field selection by FSEL-bit; 1 = automatic field detection 0 = 50 Hz (625 lines); 1 = 60 Hz (525 lines) 0 = PLL closed; 1 = PLL open, horizontal frequency fixed 0 = HCL and HSY outputs HIGH (pins 26 and 29); 1 = HCL and HSY outputs active. 0 = TV mode (slow time constant); 1 = VTR mode (fast time constant). 0 = inverted; 1 = not inverted 0 = not inverted; 1 = inverted 0 = off; 1 = on
VTRC MUIV FSIV WIND
VTR/TV mode select: MUXC signal invertion: Fast switch input signal inversion: Narrow fast switch window:
April 1993
36
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
ASTD "10" OFTS IPBP CDVI Automatic standard switching: 0 = off; 1 = on
SAA7151B
----------------- --------------------------------------------------------------------------------------------------
Select output format: External UV signal interpolation filter: Chrominance PLL filter selection for: 0 = 4 : 1 : 1 format; 1 = 4 : 2 : 2 format. 0 = active; 1 = bypassed 0 = VTR or TV source; 1 = fast time constant for FSC-PLL (only for special applications)
----------------- --------------------------------------------------------------------------------------------------
----------------- --------------------------------------------------------------------------------------------------
YDEL3 to YDEL0
Luminance delay compensation in 37 ns steps:
YDEL3 0 0 1 1 YDEL2 0 1 0 1 D6 D5 D4 D3 YDEL1 0 1 0 1 D2 D1 D0 YDEL0 0 1 0 1 gain maximum gain to DTV level to CCIR level to minimum gain ) ) ) default programmed values ) dependent on application ) ) ) ) ) delay 0 to 259 ns (step 0 to 7) -296 to -37 ns (negative delay; step -8 to
-1)
CHCV7 to CHCV0 Chroma gain reference value "11" D7
1 1 0 0
1 : 0 : 0 : 0
1 1 1 0
1 1 1 0
1 0 1 0
1 : 0 : 1 : 0
1 1 0 0
1 1 1 0
April 1993
37
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
OEDY "12" OEDC Enable Y signals on YUV-bus: Enable UV signals on YUV-bus:
SAA7151B
0 = output high-impedance; 1 = output active (dependent on FEIN) 0 = output high-impedance; 1 = output active (dependent on FEIN) VNOI1 0 0 1 1
----------------- --------------------------------------------------------------------------------------------------
VNOI1, VNOI0 Vertical noise reduction mode:
VNOI0 0 1 0 1
mode normal searching free-running bypassed
BFON BOFL2 to BOFL0
Bottom flutter compensation switching: 0 = off; 1 = on (controlled by BOFL-bit) Bottom flutter compensation BOFL2
BOFL1 0 0 1 1
BOFL0 0 1 0 1
start at line number
297 for PAL (247 for NTSC; active to end of field) 298 for PAL (248 for NTSC; active to end of field) . . 303 for PAL (253 for NTSC; active to end of field) 304 for PAL (254 for NTSC; active to end of field)
0 0 1 1
The bottom flutter circuit is able to compensate for horizontal phase jump of up to 16 s. Note: The bottom flutter gate is active at - HPLL is locked - HPLL in VTR mode - the vertical noise limiter (VNL) is in the VTR mode - gating is switched by BFON-bit = 1 (subaddress 12) Gate 2 0 1 0 1 Gate 1 0 0 1 1 HPLL function normal disabled double speed unused
vertical pulse programmable by BOFL(2-0) gate 2 000 gate 1 111
Notes 1. an internal sign-bit D8 set to HIGH indicates that all values are always negative 2. H-PLL does not operate in this condition; the system clock frequency is set to a value fixed by the last update and is within 7.1 % of the nominal frequency.
April 1993
38
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
MEH326
SAA7151B
handbook, halfpage
0
handbook, halfpage
0
MEH325
VY -6 (dB) -12 -18 -24 -30 PAL -36 -42 -48
VY -6 (dB) -12 -18 -24 -30 NTSC -36 -42 -48 0 2 4 6 fY (MHz) 8
0
2
4
6 fY (MHz)
8
Fig.22 Frequency response of chroma stop filter in colour-difference mode for 50 Hz PAL. Filter is only active in fast switching mode, but bypassed in RGB mode. The selected filter is dependent on actual detected colour standard.
Fig.23 Frequency response of chroma stop filter in colour-difference mode for 60 Hz NTSC. Filter is only active in fast switching mode, but bypassed in RGB mode. The selected filter is dependent on actual detected colour standard.
handbook, halfpage
0
MEH327
VY -6 (dB) -12 -18 -24 -30 SECAM -36 -42 -48
0
2
4
6 fY (MHz)
8
Fig.24 Frequency response of chroma stop filter colour-difference mode for 50 Hz SECAM. Filter is only active in fast switching mode, but bypassed in RGB mode. The selected filter is dependent on actual detected colour standard.
April 1993
39
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SAA7151B
handbook, full pagewidth
18
MEH309
63h 12 VY (dB) 6 43h 0 53h 73h 53h 43h
-6
63h
73h
-12
-18
-24 50 Hz PAL/SECAM; pre-filter on 0 1 2 3 4 5 6 fY (MHz) 7
-30
Fig.25 Maximum luminance peaking control as a function of four different aperture centre frequencies controllable by subaddress byte 06; aperture factor 1; coring off; chroma trap on; pre-filter on; and bandfilter on.
handbook, full pagewidth
18
MEH310
12 VY (dB) 6 43h 42h 0 41h 42h -6 40h -12 40h 41h 43h
-18
-24 50 Hz PAL/SECAM; pre-filter on -30 0 1 2 3 4 5 6 fY (MHz) 7
Fig.26 3.8 MHz luminance peaking control as a function of four different aperture factors controllable by subaddress byte 06; coring off; chroma trap on; pre-filter on and bandfilter on.
April 1993
40
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SAA7151B
handbook, full pagewidth
18
MEH311
23h 12 VY (dB) 6 13h 23h -6 13h -12 03h 33h 33h
03h
0
-18
-24 50 Hz PAL/SECAM; pre-filter off 0 1 2 3 4 5 6 fY (MHz) 7
-30
Fig.27 Maximum luminance peaking control as a function of four different aperture centre frequencies controllable by subaddress byte 06; aperture factor 1; coring off; chroma trap on; pre-filter off; and bandfilter on.
handbook, full pagewidth
18
MEH312
12 VY (dB) 6 03h 0 01h -6 00h 03h 02h 02h
-12
01h 00h
-18
-24 50 Hz PAL/SECAM; pre-filter off -30 0 1 2 3 4 5 6 fY (MHz) 7
Fig.28 4.1 MHz luminance peaking control as a function of four different aperture factors controllable by subaddress byte 06; coring off; chroma trap on; pre-filter off and bandfilter on.
April 1993
41
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
18
SAA7151B
MEH313
handbook, full pagewidth
73h
12 VY (dB) 6 43h 0 63h 53h 63h 73h 43h 53h
-6
-12
-18
-24 60 Hz NTSC; pre-filter on 0 1 2 3 4 5 6 fY (MHz) 7
-30
Fig.29 Maximum luminance peaking control as a function of four different aperture centre frequencies controllable by subaddress byte 06; aperture factor 1; coring off; chroma trap on; pre-filter on; and bandfilter on.
handbook, full pagewidth
18
MEH314
12 VY (dB) 6 41h 43h
42h
40h 41h
0
40h 42h
-6
43h
-12
-18
-24 60 Hz NTSC; pre-filter on -30 0 1 2 3 4 5 6 fY (MHz) 7
Fig.30 3.8 MHz luminance peaking control as a function of four different aperture factors controllable by subaddress byte 06; coring off; chroma trap on; pre-filter on and bandfilter on.
April 1993
42
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
18
SAA7151B
MEH315
handbook, full pagewidth
12 VY (dB) 6 33h 23h 13h 13h 03h
0
03h 23h
-6
33h
-12
-18
-24 60 Hz NTSC; pre-filter off 0 1 2 3 4 5 6 fY (MHz) 7
-30
Fig.31 Maximum luminance peaking control as a function of four different aperture centre frequencies controllable by subaddress byte 06; aperture factor 1; coring off; chroma trap on; pre-filter off; and bandfilter on.
handbook, full pagewidth
18
MEH316
12 VY (dB) 6 03h 02h 0 01h -6 00h 00h 03h 02h
-12
01h
-18
-24 60 Hz NTSC; pre-filter off -30 0 1 2 3 4 5 6 fY (MHz) 7
Fig.32 4.1 MHz luminance peaking control as a function of four different aperture factors controllable by subaddress byte 06; coring off; chroma trap on; pre-filter off and bandfilter on.
April 1993
43
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
MEH317
SAA7151B
MEH318
handbook, halfpage
24
handbook, halfpage
24
83h VY (dB) 12 81h 6 80h 0 0 6 18 82h VY (dB) 12 18
A3h A2h A1h
A0h
-6 50 Hz S-Video; chroma trap off -12 0 2 4 6 fY (MHz) 8
-6 50 Hz S-Video; chroma trap off -12 0 2 4 6 fY (MHz) 8
Fig.33 4.1 MHz luminance peaking control as a function of four different aperture factors controllable by subaddress byte 06; pre-filter off; coring off and bandpass filter on.
Fig.34 2.6 MHz luminance peaking control as a function of four different aperture factors controllable by subaddress byte 06; pre-filter off; coring off and bandpass filter on.
MEH320
MEH319
handbook, halfpage
24
handbook, halfpage
24
VY (dB)
18
83h 82h 81h
VY (dB)
18
A3h A2h
12
12
6 80h
6
A1h A0h
0
0
-6 60 Hz S-Video; chroma trap off -12 0 2 4 6 fY (MHz) 8
-6 60 Hz S-Video; chroma trap off -12 0 2 4 6 fY (MHz) 8
Fig.35 4.1 MHz luminance peaking control as a function of four different aperture factors controllable by subaddress byte 06; pre-filter off; coring off and bandpass filter on.
Fig.36 2.6 MHz luminance peaking control as a function of four different aperture factors controllable by subaddress byte 06; pre-filter off; coring off and bandpass filter on.
April 1993
44
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SAA7151B
MEH321
MEH322
handbook, halfpage
18
handbook, halfpage
18
83h 12 VY (dB) 6 80h 0 0 82h 81h 12 VY (dB) 6
8Bh 8Ah 89h 88h
-6 -12 50 Hz Y/C; all filters off -18 0 2 4 6 fY (MHz) 8
-6 -12 60 Hz Y/C; all filters off -18 0 2 4 6 fY (MHz) 8
Fig.37 4.1 MHz luminance peaking control in 50 Hz / S-VHS mode as a function of four different aperture factors controllable by subaddress byte 06.
Fig.38 4.1 MHz luminance peaking control in 60 Hz / S-VHS mode as a function of four different aperture factors controllable by subaddress byte 06.
MEH323
handbook, halfpage
24
MEH324
handbook, halfpage
24
B3h VY (dB) 12 83h 6 93h 0 B3h 6 A3h 93h 0 18 A3h 83h 93h VY (dB) 12 18 A3h
B3h 83h 93h 83h B3h A3h
-6 50 Hz Y/C; bandfilter on -12 0 2 4 6 fY (MHz) 8
-6 60 Hz Y/C; bandfilter on -12 0 2 4 6 fY (MHz) 8
Fig.39 Maximum luminance peaking control in 50 Hz / S-VHS mode as a function of four aperture centre frequencies controllable by subaddress byte 06.
Fig.40 Maximum luminance peaking control in 60 Hz / S-VHS mode as a function of four aperture centre frequencies controllable by subaddress byte 06.
April 1993
45
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
PROGRAMMING EXAMPLE
SAA7151B
Coefficients to set operation for application circuits Figures 19, 20 and 21. Values recommended for PAL CVBS input signal and 4:2:2 CCIR output signal (all numbers of the Table 6 are hex values). Table 7 Recommended default values (note 1) FUNCTION increment delay horizontal sync HSY begin horizontal sync HSY stop horizontal clamping HCL begin horizontal clamping HCL stop horizontal sync after PHI1 luminance bandwidth control: hue control (0 degree) miscellaneous controls #1 miscellaneous controls #2 PAL switch sensitivity SECAM switch sensitivity miscellaneous controls #3 miscellaneous controls #4 miscellaneous controls #5 miscellaneous controls #6 miscellaneous controls #7 nominal chrominance gain miscellaneous controls #8 VALUE (HEX) 4D 3D 0D F3 C6 FB 02 (note 2) 00 09 C0 4D 40 80 60 B4 9F C0 4F C2
SUBADDRESS BIT NAME 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 Notes IDEL(7-0) HSYB(7-0) HSYS(7-0) HCLB(7-0) HCLS(7-0) HPHI(7-0) BYPS, PREF, BPSS(1-0) BFBY, CORI, APER(1-0) HUEC(7-0) CSTD(2-0), CKTQ(4-0) OSCE, LFIS(1-0), CKTS(4-0) PLSE(7-0) SESE(7-0) FSAU, GPSI(2-1), CGFX, AMPF(3-0) COLO, CHSB, GPSW0, SUVI, SXCR, FSDL(2-0) CCIR, COEF, OEHS, OEVS UVSS, CHRS, CDMO, CDPO AUFD, FSEL, HPLL, SCEN, VTRC, MUIV, FSIV, WIND ASTD, OFTS, IPBP, CDVI, YDEL(3-0) CHCV(7-0) OEDY, OEDC, VNOI(1-0), BFON, BOFL(2-0)
1. Slave address is 8A (hex) at IICSA = LOW or 8E (hex) at IICSA = HIGH. 2. Dependent on applications (Figures 25 to 40).
April 1993
46
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
PACKAGE OUTLINE PLCC68: plastic leaded chip carrier; 68 leads
SAA7151B
SOT188-2
eD y 60 61 X 44 43 Z E A
eE
bp b1 wM
68
1
pin 1 index e
E
HE A A4 A1 (A 3)
k
9
27
k1
Lp detail X
10 e D HD
26 ZD B
vM A
vMB 0 5 scale 10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.30
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07
45 o
0.180 inches 0.020 0.01 0.165
0.930 0.930 0.995 0.995 0.048 0.057 0.021 0.032 0.958 0.958 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.13 0.890 0.890 0.985 0.985 0.042 0.040 0.013 0.026 0.950 0.950
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT188-2 REFERENCES IEC 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
April 1993
47
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
SAA7151B
Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
April 1993
48
Philips Semiconductors
Product specification
Digital multistandard colour decoder with SCART interface (DMSD2-SCART)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7151B
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
April 1993
49

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